From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan. In the Git ...

Try these RISC-V SBCs instead of Raspberry Pi for your next project.

Integrity FASTApps from Breker is a library of automated test-generation IP elements that provides high-coverage verification for RISC-V processor cores and SoCs. Specific test sets are provided for ...

SiFive's oversubscribed series G round of financing suggests the industry's historical caution around the RISC-V architecture ...

“The RISC-V instruction set architecture (ISA) is a promising open-source architecture supporting the Open Era of Computing. As RISC-V matures, consumers, industry leaders, and nation states are ...

Page 1: SiFive HiFive Premier P550: RISC-V Levels Up On Real Development Hardware SiFive HiFive Premier P550: Everything is Fine, Nothing Is Ruined The HiFive Premier P550 was perfectly trouble-free ...

With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either ...

Samsung is preparing a PCIe 5.0 SSD that pairs quad-level cell (QLC) flash memory with a RISC-V-based controller, a combination that could reshape cost and performance expectations for storage in ...