Designed a 4-bit counter using a J-K flip-flop that has a clocked input with reset. Performed simulations of various output parameters like rise time and fall time. The design is done using cadence ...

In my previous design idea, a design for a simple GPS disciplined oscillator (GPSDO) 10 MHz reference was presented. A note at the end of that article describes the realization that a frequency ...

All the advantages of solid-state design are now yours in these new hp solid state counters—offered at prices comparable to those of today's vacuum tube counters. And you get the advantages of greater ...